Browse Prior Art Database

Fast TTL Burst Controller for Microprocessor

IP.com Disclosure Number: IPCOM000119251D
Original Publication Date: 1991-Jan-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 3 page(s) / 76K

Publishing Venue

IBM

Related People

Carnevale, MJ: AUTHOR [+4]

Abstract

A method to burst-fill a Motorola 68030 processor is described. This method uses only a single XOR gate in the critical memory path which allows for a zero-wait-state implementation.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 67% of the total text.

Fast TTL Burst Controller for Microprocessor

      A method to burst-fill a Motorola 68030 processor is
described.  This method uses only a single XOR gate in the critical
memory path which allows for a zero-wait-state implementation.

      The Motorola 68030 processor supports burst-fill operation by
providing an initial address and a burst-fill request line.  External
hardware then must provide four 32-bit-long words (one at a time) to
the processor corresponding to its 16-byte internal cache line size.
These 16-byte cache lines and long word memory addresses are
organized in the manner shown in Fig. 1.

      Once the M68030 processor requests an initial address starting
at a long word boundary in a given line, the external hardware must
provide all 16 bytes of data wrapping back around to byte 0, if
necessary.

      Since the memory is addressed by long words, the 3rd and 4th
least significant bit of the address must be incremented by hardware
to address all 4 long words.  These two bits will be referred to as
address bits 02 and 03, respectively.  The table shown in Fig. 2
displays the necessary values of these bits for each 4-byte burst
access for all four possible initial address values.

      Looking at the table a different way, the values of the 2nd,
3rd and 4th access can be expressed as either being inverted from the
original value or not.

      Examining the chart shown in Fig. 3, it can be seen that
address bit 2 is simply inver...