Browse Prior Art Database

Scan Ring Tap

IP.com Disclosure Number: IPCOM000119256D
Original Publication Date: 1991-Jan-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 3 page(s) / 96K

Publishing Venue

IBM

Related People

Marquart, DW: AUTHOR

Abstract

When several chips using LSSD scan test are daisy-chained on a package with restricted I/O pins, such as a multiple chip module, it is difficult to determine the location of a break in the scan path. Adding "taps" to the scan path (read-access points between chips in the ring) allows for isolating the chip causing the failure of the scan path. The taps cannot be common I/O (able to drive or read the data) because that would violate LSSD rules, but a simple read connection does not violate the rules. (See Fig. 1; this uses three pins as opposed to the four required for separate scan paths.) This method, when used in conjunction with the method disclosed in U.S.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Scan Ring Tap

      When several chips using LSSD scan test are daisy-chained
on a package with restricted I/O pins, such as a multiple chip
module, it is difficult to determine the location of a break in the
scan path.  Adding "taps" to the scan path (read-access points
between chips in the ring) allows for isolating the chip causing the
failure of the scan path. The taps cannot be common I/O (able to
drive or read the data) because that would violate LSSD rules, but a
simple read connection does not violate the rules.  (See Fig. 1; this
uses three pins as opposed to the four required for separate scan
paths.)  This method, when used in conjunction with the method
disclosed in U.S. Patent 4,298,980, allows for complete isolation of
scan path failures without requiring separate scan paths for each
chip and uses only N+1 package pins (where N is the number of chips
in the chain), as opposed to 2N package pins for separate scan paths.
The above-referenced patent describes setting known 1 and 0 values
into known positions in the scan path so that the pattern can be
recognized when the chip is scanned; the pre sence or absence of the
pattern in the scanned-out data allows for isolation of problems.
The scan tap invention allows for the isolation of problems to the
chip rather than to the connection between two chips where it is not
known whether the driver of the first chip or the receiver of the
second chip has failed.

      Fig. 2 shows the tap invention for several chips in a scan
ring.  This uses 5 pins as opposed to the 8 required for a separate
scan path for each chip.

      The tap invention, when used with the 1/0 pattern method
described earlier, provides almost the same amount of error isolation
as a separate scan path for each chip.  A separate scan path allows
the tester to see the 1/0 pattern come out, which helps isolate
faults to chip inputs and outputs.  In the two-chip-with-tap case,
the tester can see the 1/0 pattern come from both chips, which allows
isolation of faults in the...