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Improved Method for Complement/Recomplement Error Correction

IP.com Disclosure Number: IPCOM000119258D
Original Publication Date: 1991-Jan-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Hovis, WP: AUTHOR [+2]

Abstract

Described is a technique for improving the effectiveness of extended error correction (or complement retry). The improvement is obtained by driving the original data onto the data bus between the store of complement data and the fetch of complement data. This will cause open lines or tristate modules to appear as hard errors instead of soft errors. At least one of the two errors detected must appear hard in order for extended error correction to correct the data.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

Improved Method for Complement/Recomplement Error Correction

      Described is a technique for improving the effectiveness
of extended error correction (or complement retry).  The improvement
is obtained by driving the original data onto the data bus between
the store of complement data and the fetch of complement data.  This
will cause open lines or tristate modules to appear as hard errors
instead of soft errors.  At least one of the two errors detected must
appear hard in order for extended error correction to correct the
data.

      Extended error correction can be improved by re-driving
original data onto the data bus between the store of complemented
data and the read of complemented data.  This would cause the open
socket or tristate module data bus to be read bad on the read or
fetch of complemented data. Also, if a line were open to the clamp
resistor, it would also cause it to look like a hard error.  No
degradation should occur for the situation where a clamp already
exists. One must provide enough time for the clamp to be consistently
read as a '1' or a '0' for it (the clamp) to be effective in
detecting opens or tristates as hard errors. This would, therefore,
be an additional design constraint of the improved error correcting
scheme.  An example of how this scheme would work on a 16-bit data
field is shown below.
         Data Expected
         0000000000000000
         Data read (double bit error)
         0100000100000000
          .     .
         Store of Complement Data
          .     .
         1011111011111111
          .     .
         Data bus driven to original data value
          .     .
         0100000100000000
      ...