Browse Prior Art Database

Interchangeable I/O Cell for Gate Array

IP.com Disclosure Number: IPCOM000119270D
Original Publication Date: 1991-Jan-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 3 page(s) / 89K

Publishing Venue

IBM

Related People

Ning, TH: AUTHOR [+2]

Abstract

Presently, all basic cells of gate arrays are designed so that the input and output ports of each gate (or cell) are located at fixed positions and can only be reached by fixed channels. The input and output channels cannot be interchanged. To connect the output of one gate to the input of another gate, wire must be bent more than once (at least), and wire bending consumes many channels. In a TTL gate array (Fig. 1), the input ports 11 are located at the emitter of the input transistor while the output port 12 is the collector of the output transistor. If the wires of the first level metal run vertically, a second level is needed just to make a simple connection from the output of gate #2 13 to the input of gate #1 11.

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Interchangeable I/O Cell for Gate Array

      Presently, all basic cells of gate arrays are designed so
that the input and output ports of each gate (or cell) are located at
fixed positions and can only be reached by fixed channels.  The input
and output channels cannot be interchanged.  To connect the output of
one gate to the input of another gate, wire must be bent more than
once (at least), and wire bending consumes many channels.  In a TTL
gate array (Fig. 1), the input ports 11 are located at the emitter of
the input transistor while the output port 12 is the collector of the
output transistor.  If the wires of the first level metal run
vertically, a second level is needed just to make a simple connection
from the output of gate #2 13 to the input of gate #1 11.

      An interchangeable I/O channel cell for a gate array will be
wire-efficient, i.e., less wiring will be required to wire such
gates.  An input or output port can be on any channel.  There is no
need to change the Si-layout to realize such a gate.  The cell is
made up of one or more MTL gates.  The I/O channel is defined only by
the contact hole mask.  Thus, any channel can be an input or output
channel, enabling the connection of output of one gate to the input
of another gate without having to bend the wire. Consequently, less
channels are required to wire such gates (Fig. 2).

      The Si circuits up to the emitter poly level are processed
exactly the same way as all transistors a...