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CMOS Four-Input Selector

IP.com Disclosure Number: IPCOM000119288D
Original Publication Date: 1991-Jan-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 109K

Publishing Venue

IBM

Related People

Letreguilly, M: AUTHOR [+4]

Abstract

The principle of a four-input selector circuit is shown in Fig. 1 bearing reference 100. As apparent from Fig. 1, circuit 100 can be split into two parts: a BUFFER 101 which gives the driving capability to the controls and the SELECTOR circuit 102 which selects one data out of four data in.

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CMOS Four-Input Selector

      The principle of a four-input selector circuit is shown
in Fig. 1 bearing reference 100. As apparent from Fig. 1, circuit 100
can be split into two parts: a BUFFER 101 which gives the driving
capability to the controls and the SELECTOR circuit 102 which selects
one data out of four data in.

      Right combinations of the control lines S0 and S1 select the
required data input out of A0, B0, C0 and D0 to the output 10. Note
also, that this circuit applies for a one-bit Selector as well as for
a n-bit Selector.

      Let us assume that we want to select one data out of A0, B0,
C0 and D0. Two control signals S0 and S1 are required.
The logical function of a 4:1 SELECTOR can be then defined as:
10 = A0.S0-- .S1--+ B0.S0.S1 -- + C0.S0-- . S1 + D0.S0. S1 >

      The details of buffer circuit 101, which is, in fact comprised
of two independent buffers 101A and 101B, are shown in Fig. 2. The re
quired buffering is given by two separate sets of inverters to
deliver the true and complement values of the control lines.
Transistors TN01/ TP01 to TN03/TP03 and TN04/TP04 to TN05/TP05
provide, respectively, the P1 and  P0 buffered lines built from the
S0 control input.

      Similarly, transistors TN06/TP06 to TN08/TP08 and TN09/TP09 to
TN10/TP10 provide, respectively, the Q1 and Q0 buffered lines built
from the S1 control input.
P0 = S0  ;  P1 = S1--
Q0 = S1  ;  Q1 = S0--

      Note that the buffer logic is kept as minimum as possible to
gain delay of decoder; this will then improve the performance of the
overall function. In typical applications, the critical path of a
Selector is the time required to get the data at the output after...