Browse Prior Art Database

Self-Calibrating Adjustable-Time Digital Delay

IP.com Disclosure Number: IPCOM000119292D
Original Publication Date: 1991-Jan-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 135K

Publishing Venue

IBM

Related People

Hunt, WJ: AUTHOR [+2]

Abstract

This article describes a method to electronically select the proper number of NAND pair delay blocks to connect to produce the desired delay time. This method provides a digital, on-chip, adjustable delay line which is tolerant of gate delay time variations due to manufacturing tolerances, operating temperature and voltage. This is accomplished by periodically measuring the average delay time of the NAND pair block using an on-chip ring oscillator circuit. The desired delay time of the string may be selected by modifying the contents of a latch, and the invention provides accuracy approaching the desired time +/- one max NAND delay time.

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Self-Calibrating Adjustable-Time Digital Delay

      This article describes a method to electronically select
the proper number of NAND pair delay blocks to connect to produce the
desired delay time.  This method provides a digital, on-chip,
adjustable delay line which is tolerant of gate delay time variations
due to manufacturing tolerances, operating temperature and voltage.
This is accomplished by periodically measuring the average delay time
of the NAND pair block using an on-chip ring oscillator circuit.  The
desired delay time of the string may be selected by modifying the
contents of a latch, and the invention provides accuracy approaching
the desired time +/- one max NAND delay time.

      Fig. 1 shows the major elements of this method.  The
CALIBRATION SEQUENCER controls the state of the remaining elements.
Calibration is initiated by START CAL and halted and returned to a
Delay function by INTRPT CAL.  The SYSTEM CLOCK supplied to the
CALIBRATION SEQUENCER is used not only to clock the sequencer state,
but also as a reference clock for the calibration.  The input to the
Delay is DLY IN and DLY/ OSC OUT is the delayed output when the
circuit is in Delay mode.  The details of this invention's operation
are described below.  The operation is based upon a delay measurement
technique using an extension of the circuit shown in Fig. 2.

      The REFERENCE COUNTER counts the sequence from 0 to Nr, the
terminal count.  The MEASUREMENT COUNTER is allowed to count when the
REFERENCE COUNTER is enabled, thus it counts from 0 to Nm.  The
SYSTEM CLOCK has a known period Tr and is used as a time reference.
Inaccuracy of Tr used for calibration will cause inaccuracy in the
delay time obtained by the invention.  The RING CLOCK is a clock
generated by a string of non-inverting buffers with the inverted
output fed back to the input.  Ring oscillator circuits of this type
are shown [*, chapter 7].  The CLEAR input is held at logic 0 for a
period of time sufficient to bring all q buffers to a stable logic 1
state, then deasserted to allow the RING CLOCK circuit to oscillate.
The period of RING CLOCK is a function of the delay time of the
buffers and the inverting block.  If the delay of the NAND is
one-half the delay of a BUFFER BLOCK, and the rise and fall delays
are equal, then the period of the RING CLOCK Tm is given by the
following equation:
 Tm = 2 ( q + 0.5 ) td
where  q    is the number of BUFFER BLOCKs in the string, and
 td   is the input to output delay time of a BUFFER BLOCK
Let Te be the time in nanoseconds that the counters are enabled.
Thus:
 Te = Nr * Tr = Nm * Tm + Em * Tm
where  Nr   is the terminal count on the REFERENCE COUNTER,
        Tr   is the SYSTEM CLOCK period in nanoseconds,
        Nm   is the count when the MEASUREMENT COUNTER is stopped,
        Tm   is the RING CLOCK period in nanoseconds, and
        Em   is the fractional count error of the MEA...