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Phase Shift Circuit for High Speed Clock

IP.com Disclosure Number: IPCOM000119298D
Original Publication Date: 1991-Jan-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 3 page(s) / 58K

Publishing Venue

IBM

Related People

Asada, S: AUTHOR [+3]

Abstract

Disclosed is a circuit for phase shift of high-speed clock using gate delay of LSI. This circuit can control the phase shift value dynamically and keep it the settled value regardless of variations of gate delay which are caused by process variations or operating environment of LSI. Fig. 1 shows the function block diagram of this circuit.

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Phase Shift Circuit for High Speed Clock

      Disclosed is a circuit for phase shift of high-speed
clock using gate delay of LSI.  This circuit can control the phase
shift value dynamically and keep it the settled value regardless of
variations of gate delay which are caused by process variations or
operating environment of LSI.  Fig. 1 shows the function block
diagram of this circuit.

      At first the base clock passes through the N stages delay lines
and latches each output of all stages (DELAY-1 to N), and it is as
sumed that all latches (LT-1 to LT-N) are rising edge-triggered type.
If the delay of a stage is smaller than half cycle of the base clock,
the latched output stays low, and, if not, it stays high.  The
pattern of all latched outputs indicates the degree of the gate delay
because this pattern will be changed in accordance with gate delay.
Based on this pattern, a suitable delayed clock is selected as a
shifted clock.  Therefore, this circuit can keep the difference
between the settled value and the shifted value minimum regardless of
the static and dynamic variations which are caused by process
variations or operating environment of LSI.

      The case which required the 1/4 cycle shifted clock is shown in
Fig. 2.  In this case, the circuit selects the delayed clock of stage
DELAY-m/2 (DELAY-m+1/2, when 'm' is an odd number) when the latched
outputs from LT-1 to LT-m stay low and the latched outputs after LT-
m+1 stay high.  For example,...