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Exponential Delta Timer

IP.com Disclosure Number: IPCOM000119300D
Original Publication Date: 1991-Jan-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Floryance, GG: AUTHOR

Abstract

Described are two techniques for reducing the cost and quantity of logic needed to time stamp a sampled event.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 62% of the total text.

Exponential Delta Timer

      Described are two techniques for reducing the cost and
quantity of logic needed to time stamp a sampled event.

      In many test environments, it is necessary to time-stamp events
which are being monitored.  Traditionally, a timer is used which
increments at a fixed rate with the timer value being stored in RAM
when an event occurs.  If the required sample rate is very fast and
the sample time is very large, the width (number of stages) of the
timer and the width of the RAM in which the value is stored become
large.

      This article offers an alternative to the traditional fixed
rate technique.  The figure illustrates the hardware used.  An
oscillator (OSC) drives the clock input of the CLOCK COUNTER which
generates 'n' number of clocks, each running at 1/2 the frequency of
the previous clock.  A timer clock (CLOCK) is selected by the
multiplexer (MPX) which is controlled by the TIMER EXPONENT lines and
is used to clock both the TIMER VALUE COUNTER and the TIMER EXPONENT
COUNTER. The TIMER VALUE and TIMER EXPONENT are each 1-byte values
which will be stored in the RAM when an event occurs.  The CARRY line
from the TIMER VALUE COUNTER goes to the CHIP ENABLE input of the
TIMER EXPONENT COUNTER.  The common RESET line clears the counters to
zero after an event is recorded.

      During operation, the CLOCK line is progressively slowed based
upon the TIMER EXPONENT VALUE which is controlling the MPX select
lines.  Ini...