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Multiprocessor Dynamic Test Method

IP.com Disclosure Number: IPCOM000119308D
Original Publication Date: 1991-Jan-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 73K

Publishing Venue

IBM

Related People

Wu, RH: AUTHOR

Abstract

Disclosed is a method to dynamically test a multiprocessor system which consists of six processors and four pieces of memory. The six processors are master (M), pipe #1 (P1), pipe #2 (P2), pipe #3 (P3), pipe #4 (P4) and backend (B). Memory #1 (MEM1) is shared by host and M, and memory #2 (MEM2) is shared by M and P1. Memory #3 (MEM3) is shared by P2 and P3, and memory #4 (MEM4) is shared by P4, B and M. The primary users of MEM1, MEM2, MEM3 and MEM4 are M, P1, P3 and B, respectively.

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This is the abbreviated version, containing approximately 52% of the total text.

Multiprocessor Dynamic Test Method

      Disclosed is a method to dynamically test a
multiprocessor system which consists of six processors and four
pieces of memory.  The six processors are master (M), pipe #1 (P1),
pipe #2 (P2), pipe #3 (P3), pipe #4 (P4) and backend (B). Memory #1
(MEM1) is shared by host and M, and memory #2 (MEM2) is shared by M
and P1.  Memory #3 (MEM3) is shared by P2 and P3, and memory #4
(MEM4) is shared by P4, B and M. The primary users of MEM1, MEM2,
MEM3 and MEM4 are M, P1, P3 and B, respectively.

      This dynamic test method is based on a bus arbitration scheme
and an interprocessor communication protocol.  The bus arbitration
scheme has the following rules:  (1) there is a base unit of time
called Base Off Bus Time (BOBT) that a processor has to relinquish
its access of the bus; (2) a Priority Level (PL) is given to each
processor that shares a resource on the bus; (3) after accessing the
bus, each processor has to get off the bus for at least a period of
time called Off Bus Time (OBT); and (4) when there are N processors
sharing a resource on the bus, the OBT of each processor equals (N -
PL + 1) x BOBT.

      For any two processors sharing a memory, there are two buffers
allocated at designated locations in the memory for interprocessor
communication.  Those signals going from M to the other processors
are called TAPOUTs, and those coming to M from the other processors
are called TAPINs.  The protocol between M and one of the other
processors, for instance, P1, works like this:  (1) M writes a
command into buffer #1 and signals TAPOUT to P1, then gets off the
bus for OBT period of time and waits on the TAPIN signal; (2) on
receiving TAPOUT, P1 reads buffer #1 and carries out the command,
then writes a return...