Browse Prior Art Database

Method for Optimizing Clock Trees On VLSI Chips

IP.com Disclosure Number: IPCOM000119321D
Original Publication Date: 1991-Jan-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 117K

Publishing Venue

IBM

Related People

Doyle, JJ: AUTHOR [+3]

Abstract

Described is a means of optimizing the wire length used for implementing clock repowering trees on VLSI chips and balancing the wiring capacitance on equivalent clock copies, thereby minimizing arrival skew at the latches on-chip.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Method for Optimizing Clock Trees On VLSI Chips

      Described is a means of optimizing the wire length used
for implementing clock repowering trees on VLSI chips and balancing
the wiring capacitance on equivalent clock copies, thereby minimizing
arrival skew at the latches on-chip.

      This method optimizes parallel repowering trees on a chip by
using simulated annealing.  Simulated Annealing is the optimization
algorithm described in U.S. Patent 4,495,559.

      Each net consists of one output pin and one or more input pins.
Input pins that are driven by logically equivalent nets are logically
clustered based on physical proximity.  Input pins that are close
together will tend to be driven by the same output pin.  The driver
book containing this output pin is moved near the "RC centroid" (see
below) of the input pins that it drives, in order to facilitate
balanced wiring of the net. RC Centroid:  Concept and Method of
Calculation

      The RC centroid of a net is the point at which the driver of
the net should be placed in order to minimize the wiring delay due to
Resistance and Capacitance (hence "RC") from the driver to all input
pins in the net.  The RC centroid is estimated as follows:

      The magnitude of the capacitances of the input pins, as well as
the physical locations of those pins, were deemed to be the main
considerations for determining the RC centroid, since the wiring used
to connect the net is fairly uniform in resistance and capacitance.
Thus, the location of the RC centroid was calculated as a standard
geometric centroid, except the location of each input pin was
weighted by the magnitude of its capacitance (see Fig. 1).

      A sample calculation will reveal that the RC centroid migrates
toward an input pin as its capacitance increases.

      Fig. 2 shows the placement of a group of equivalent nets
immediately after initial placement and before any clock tree
optimization.  The black squares denote clock driver output pins.
The white squares denote latch input pins.  A line is drawn from each
output pin to each of the input pins that it drives.  These
connections are as provided in the original design netlist for the
connection of clock repowering circuits to latches.

      Fig. 3 shows the result of optimizing the same group of
equivalent...