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High Power LSI Performance Optimizer

IP.com Disclosure Number: IPCOM000119335D
Original Publication Date: 1991-Jan-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Koiwa, A: AUTHOR

Abstract

Disclosed is a technique to optimize LSI performance by controlling a clock frequency using thermal negative feedback. The temperature of a junction (Tjc) is determined by consumption power (P), thermal resistance (@), and the temperature of a surface (Tsuf), as follows: Tjc = @ * P + Tsuf --------- (1)

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High Power LSI Performance Optimizer

      Disclosed is a technique to optimize LSI performance by
controlling a clock frequency using thermal negative feedback.  The
temperature of a junction (Tjc) is determined by consumption power
(P), thermal resistance (@), and the temperature of a surface (Tsuf),
as follows:
      Tjc = @ * P + Tsuf   --------- (1)

      Generally, the consumption power (P) is defined as follows:
      P = C * F * V**2     --------- (2) where C   :    Constant
      F   :    Clock frequency
      V   :    Driving voltage
      V**2:    Square of V

      In order to keep Tjc under a limit value, @ is required to be
reduced (using a heat sink or a fan, etc.).  But, when it is not
possible to reduce the value of @, the F (clock frequency) is to be
reduced.  This results in a decrease of the system performance.
While the influence caused by the frequency variety is rather small
compared to the influence caused by the variety of the V, it is not
permitted to vary the V value in a large range.

      The disclosed technique is to optimize LSI performance
dynamically by feeding back Tsuf in order to vary the F and to
provide a good system performance environment.  This is accomplished
by putting the thermal probe on LSI and providing negative feedback
to the F clock.