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Quantatively Measuring the Quality of Design Verification Tests

IP.com Disclosure Number: IPCOM000119349D
Original Publication Date: 1991-Jan-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 5 page(s) / 132K

Publishing Venue

IBM

Related People

Schlipf, T: AUTHOR

Abstract

For adequately verifying the logical correctness of a VLSI chip, a large number of design verification tests (test cases) are required which produce the stimuli and check the response of the chip. The quality of the design is closely linked to the quality of the verification tests.

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Quantatively Measuring the Quality of Design Verification Tests

      For adequately verifying the logical correctness of a
VLSI chip, a large number of design verification tests (test cases)
are required which produce the stimuli and check the response of the
chip.  The quality of the design is closely linked to the quality of
the verification tests.

      Therefore, it is essential to quantitatively measure the
quality of such tests and to guide the development of further tests,
if needed.  All known approaches are computationally too expensive to
be practicable.  This problem could be largely overcome by
concentrating on the control logic of a chip.

      The new method focusses on the product terms of finite state
machines (FSMs) and the determination of the percentage of product
terms activated during simulation. The influence of simulation
performance is negligible.

      For observing the product terms of the FSM, the following
"hardware" facilities, which are used only for simulation, are added:
      o    A master and a slave register bit are assigned to each
product term of each output signal.  If the product term is activated
to '1', the associated bit is set.  Feedback of the bit to the data
input ensures that the bit remains set.
      o    A master and a slave register bit are assigned to each
product term of the state transition equations.  If the product term
is activated to '1', the associated bit is set.  Feedback of the bit
to the data input ensures that the bit remains set.
      o    Care is taken that the register bits are known only to the
simulator and that they do not generate hardware.
      o    Th...