Browse Prior Art Database

High-Speed Direct Memory Access Control Method

IP.com Disclosure Number: IPCOM000119354D
Original Publication Date: 1991-Jan-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 3 page(s) / 85K

Publishing Venue

IBM

Related People

Kumagai, M: AUTHOR [+2]

Abstract

This article describes a method for Direct Memory Control and Memory structure which can provide the high-speed data transfer between System Memory and Video Memory that is generally used for Microprocessor System board of the Personal Computer.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 54% of the total text.

High-Speed Direct Memory Access Control Method

      This article describes a method for Direct Memory Control
and Memory structure which can provide the high-speed data transfer
between System Memory and Video Memory that is generally used for
Microprocessor System board of the Personal Computer.

      In case of ordinal personal computer, the data transfer between
memory and memory was done by commercial DMA (Direct Memory Access)
Controller chip or MOVE STRING instruction of MPU (Micro Processor
Unit).  To speed-up the data transfer speed, there were two ways.
One is to expand DATA BUS width; the other way is to speed-up MPU
operation speed. But, to speed-up MPU speed DRAM (Dynamic
Random-Access Memory) speed also needs to be higher.  So MPU speed-up
is dependent on semiconductor technology.  On the other hand, to
expand DATA BUS width system board will become bigger and very
complicated.

      The purpose of this invention is to get the memory structure
and DMA (Direct Memory Access) control method which provide speed-up
of the data transfer between memory and memory without using MPU
speed-up or system DATA BUS expansion.

      Fig. 1 indicates the system structure of this invention.  This
invention consists of DMA (Direct Memory Access) controller 1,
address multiplexer 2, which switches the MPU address BUS and the
address that is produced by DMA controller, system memory 3, and
video memory 4.  The address BUS of the system memory and video
me...