Browse Prior Art Database

Latching Receiver

IP.com Disclosure Number: IPCOM000119355D
Original Publication Date: 1991-Jan-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Ludwig, T: AUTHOR [+3]

Abstract

This article describes a latching receiver which stores the last active input value of a tristate net.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 92% of the total text.

Latching Receiver

      This article describes a latching receiver which stores
the last active input value of a tristate net.

      This value is fed back to the net and the receiver output.  The
receiver also serves as a high-impedance driver, and no DC current is
required for holding the input value at a CMOS tristate net.  An
external change current is required to compensate for the latch
holding current before the complement logic state is stored.  If the
net is in a tristate mode, the latching receiver avoids a net drift
into another logic state depending upon environmental conditions. The
receiver has a high noise immunity in both logic states and allows
testing a net which is not accessible by pads. The described circuit
replaces chip external terminators, thus reducing the cost of the
functional unit.

      The figure shows the latching receiver circuit comprising a
connection of the gate of transistor 3 to the gate of transistor 2.
It is also possible to connect the gate of transistor 3 to the gate
of transistor 1.  Transistor 2 serves as an electrostatic discharge
protection means if the potential at D10 is higher than VH and
transistors 1 and 3 are used for test purposes only.  The preload
input PRL, connected to the gate of transistor 1, is negatively
active during the testing of a tristate mode net.

      During operation, transistors 5 and 6 or 4 and 7 latch the
state of receiver input RA0.  This avoids an undefined internal logic
sta...