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Controlling RC Delay in Chip Placement

IP.com Disclosure Number: IPCOM000119368D
Original Publication Date: 1991-Jan-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 64K

Publishing Venue

IBM

Related People

Jepsen, DW: AUTHOR [+3]

Abstract

Disclosed is a method for generating source-sink length targets (upper bounds) for every source-sink segment of the nets in a chip so that placement and wiring procedures which produce lengths less than or equal to these target lengths thereby guarantee that the chip will meet timing requirements. These procedures can lengthen source-sink segments with large targets, as well as can shorten critical ones with small targets. This method extends the slack allocation procedure for nets described in [*] to source-sink slack allocation.

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Controlling RC Delay in Chip Placement

      Disclosed is a method for generating source-sink length
targets (upper bounds) for every source-sink segment of the nets in a
chip so that placement and wiring procedures which produce lengths
less than or equal to these target lengths thereby guarantee that the
chip will meet timing requirements.  These procedures can lengthen
source-sink segments with large targets, as well as can shorten
critical ones with small targets. This method extends the slack
allocation procedure for nets described in [*] to source-sink slack
allocation.

      The method described examines each path through the logic
network in turn, from the one with smallest (perhaps negative) slack
to the one with the largest slack, and assigns increased or decreased
delays to each source-sink segment along the path so that the
resulting slack along the path is zero to within some small
tolerance.  After the delay targets for the more critical sinks on
all the nets have been worked out, delay targets for the other sinks
are worked out so that no signal is expected to arrive at any circuit
earlier or later than required. Target (RC) delays for each
source-sink segment are assigned so that each source-sink segment has
a target delay value.

      In the figure, a net with a fan-out of N to N sinks is
shown. Let C be the lumped capacitance of the net; C1,..., CN be the
gate capacitances respectively of the sinks sink 1, ..., sink N;
R1,..., RN be the res...