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Electronic Fault Insertion for Fault Simulation

IP.com Disclosure Number: IPCOM000119370D
Original Publication Date: 1991-Jan-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 167K

Publishing Venue

IBM

Related People

Huisman, LM: AUTHOR [+3]

Abstract

Fault simulating complex boards is as yet infeasible because of the inordinately long simulation times involved. These long simulation times are caused both by the complexity of the boards in question and by the long test sequences employed today for ICT (In Circuit Test) and FT (Functional Test). Even with the relatively small number of faults involved - typically several thousand - simulation should proceed at speeds close to the functional speed of the board itself to make a complete simulation of all the faults and of the complete test sequences feasible.

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Electronic Fault Insertion for Fault Simulation

      Fault simulating complex boards is as yet infeasible
because of the inordinately long simulation times involved.  These
long simulation times are caused both by the complexity of the boards
in question and by the long test sequences employed today for ICT (In
Circuit Test) and FT (Functional Test).  Even with the relatively
small number of faults involved - typically several thousand -
simulation should proceed at speeds close to the functional speed of
the board itself to make a complete simulation of all the faults and
of the complete test sequences feasible.

      Such fast simulations can be done by inserting the faults
manually on the board and by simulating the complete test on such a
faulted board; the faults are inserted one at a time and the test set
is simulated once for each fault. This makes the simulation fast but
merely replaces the unacceptable long simulation times by equally
unacceptable long fault-insertion times.

      The invention described here is a new technique for
electronically inserting the faults under external control. This
makes the fault-insertion times insignificant compared to the fault
simulation times.  The cost is a small increase in the fault
simulation times itself, compared to the solution with the manually
inserted faults.  We will first describe the general approach to
electronic fault insertion. The electronic fault-insertion uses
special-purpose logic chips that will be described next.

      Electronic Fault-Insertion Electronic fault-insertion is done
by modifying the board.  First, all the logic chips on the board on
whose inputs and outputs faults have to be inserted are removed from
the board.  These chips will be called the functional chips.  They
are then replaced by special-purpose chips, that we will call
sandwich chips for reasons that will become clear shortly.  These
sandwich chips have two characteristics.  The first one is, of
course, the logic that they contain.  This logic will be described in
the next section.  The second characteristic concerns the pins on the
chip package.  There are, in fact, three sets of pins.  The first set
is on the bottom and has the same geometric layout as the pin set on
the bottom of the functional chip that it replaces.  The second set
is on the top and has the same geometric layout as that of the pin
connections on the board where the functional chip was placed.  The
third set provides for control inputs to the sandwich chips and will
be discussed in the final section.

      The overall structure is shown in Fig. 1.  The functional chip
is on the top and the sandwich chip is in between the functional chip
and the board.  All bottom pins of the sandwich chip are connected to
their counterparts on the top, providing a straight electrical
connection for the pins of the functional chip to their usual
connections on the board.

      After all the functional chi...