Browse Prior Art Database

Static Flow Analysis Logic Design Aid

IP.com Disclosure Number: IPCOM000119384D
Original Publication Date: 1991-Jan-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 5 page(s) / 215K

Publishing Venue

IBM

Related People

Nakoski, J: AUTHOR

Abstract

Static Flow Analysis (SFA) is the process of analyzing software without executing it, thus finding bugs early, before laborious "dynamic" testing is begun. SFA can also be used to check VLSI hardware designs that are specified in a hardware description/simulation language.

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This is the abbreviated version, containing approximately 27% of the total text.

Static Flow Analysis Logic Design Aid

      Static Flow Analysis (SFA) is the process of analyzing
software without executing it, thus finding bugs early, before
laborious "dynamic" testing is begun.  SFA can also be used to check
VLSI hardware designs that are specified in a hardware
description/simulation language.

      To analyze a design with methodology available in recent years
involves many time-consuming steps.  Cycle simulation is the use of
an executable software model to test the function of the design.  The
software model is coded in a Register Transfer Language.  Enhanced
Functional Simulator (EFS) provides the environment for executing a
model.  This model corresponds to the hardware that is being
designed.  Stimuli to the model can be provided by Processor Control
Language (PCL) test cases.  These test cases correspond to the
external environment in which the hardware is expected to operate.

      Logic Synthesis is the automatic conversion of a functional
level hardware specification into a logic-gate level realization.
The Logic Synthesis System (LSS) is used to convert the model into a
Basic Design Language for Structure language representation.  This
gate-level representation allows for timing analysis to be done on
the function.

      The hardware design cycle used to produce the chips starts with
high-level functional specifications, timing requirements, and data-
flow diagrams.  Once these are complete, a software model of the
functions is created using the BDL/CS language.  This model is
executed with EFS to verify that the functions are correct.  The
BDL/CS model is also run through LSS to get BDL/S.  The BDL/S is run
through various timing analysis programs to verify that the timing is
correct.  Once both the function and the timing are verified, the
logic design is complete.  Next comes the physical design (placement
and wiring) of the chip. Finally, the chip is actually fabricated,
tested, and returned to the logic designers.

      Often there are problems with the hardware design cycle.  When
functional bugs are detected in the BDL/CS model, or timing problems
are detected during logic synthesis or physical design, the entire
cycle must be restarted from the BDL/CS coding phase.  Then, the
design must again proceed through a simulation, synthesis, timing,
placement, and wiring.  Typically, many iterations are required
before the design is satisfactory.  Some of these iterations are
inevitable because:
-    It is difficult to predict the exact nature of the LSS
      conversion into a gate-level realization, and the
      effect that this conversion will have on the timing of
      the logic circuit.
-    It is difficult to design a logic function that is
     perfect without going through some simulation first. -
Sometimes there are changes in the high-level
      specification, and the logic design has to be modified
      to reflect th...