Browse Prior Art Database

Multiple Clock Support of the Tramps/2 Model

IP.com Disclosure Number: IPCOM000119389D
Original Publication Date: 1991-Jan-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 3 page(s) / 131K

Publishing Venue

IBM

Related People

Genduso, TB: AUTHOR [+4]

Abstract

In most timer simulation models all components (processors, caches, memories, etc.) operate at a single clock frequency. This single clock is referred to as the system clock. A problem arises in the use of timer simulation models when modeling systems in which a single system clock frequency cannot be used because two or more components of the system are operating at different clock frequencies.

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Multiple Clock Support of the Tramps/2 Model

      In most timer simulation models all components
(processors, caches, memories, etc.) operate at a single clock
frequency. This single clock is referred to as the system clock.  A
problem arises in the use of timer simulation models when modeling
systems in which a single system clock frequency cannot be used
because two or more components of the system are operating at
different clock frequencies.

      To solve this problem a unique technique is demonstrated which
includes the following two features.
    The use of an event chain for the modeling of systems with
multiple clocks.
    The algorithm for the construction of the event chain.

      The TRAMPS/2 model will be used as an example of a timer
simulation model to which the techniques of multiple clock support
can be applied.  However, the techniques illustrated here are not
unique to the TRAMPS/2 implementation and can, therefore, be
incorporated into other timer simulation models.  The TRAMPS/2 model
divides each system clock cycle into two half cycles.  Therefore, in
the TRAMPS/2 model, the frequency of the model clock is twice the
frequency of the clock of the system being modeled.  For example,
when TRAMPS/2 is used to model a 40 MHz system, the model clock is
operating at 80 MHz.

      The system, which is illustrated in the figure, is to be
modeled.  The system uses two independent clocks.  The first clock,
'CLOCK A' is for the PROCESSOR, CACHE and INTERFACE and operates at
50MHz.  A second clock, 'CLOCK B', operates at 40 MHz and is for the
INTERFACE and MEMORY.

      As shown in the figure, the only component which is directly
affected by the two system clocks is the INTERFACE unit.  All other
components in the system are not affected by the fact that there are
two clocks in the system since all the other components are accessed
by only one of the clocks.

      The basis of the multiple clock support of the TRAMPS/2 model
is to have the clock of the model INTERFACE run at a frequency which
is a common whole multiple of the different frequencies of the clocks
of the system which is being modeled.  Since TRAMPS/2 normally uses a
clock which runs every half cycle, the model clock will therefore
operate at a frequency which is twice that of the least common whole
multiple.

      To illustrate, sampling a 400 MHz model clock every eight clock
cycles will generate a 50 MHz clock signal. Similarly, sampling the
same model clock every ten clock cycles will produce a 40 MHz clock
signal.  Each of these samplings may be divided by 2 to produce half-
cycles as well.  Also, given these numbers, every 40 cycles of the
model clock, the pattern of clock signals for both clocks will
repeat, consisting of a pattern of five 50 MHz signals and four 40
MHz signals (or 10 half-cycle and 8 half-cycle signals).  This
repeating pattern represents one ITERATION of the clock sequence.

      The mo...