Browse Prior Art Database

Circuit Packaging Enhancement

IP.com Disclosure Number: IPCOM000119404D
Original Publication Date: 1991-Jan-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 84K

Publishing Venue

IBM

Related People

Fritz, RA: AUTHOR [+2]

Abstract

Present design level packaging density allows a plurality of card assemblies, at a nominal 500 I/O pins per card assembly, to be positioned within a package but intrinsic to zero insertion force (ZIF) connectors. This concept provides the flexibility of design to allow an increased card assembly count by permitting a plurality of additional card assemblies to be connected external to the package. The cards within the assembly (not shown) are maintained in position by ZIF connectors.

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This is the abbreviated version, containing approximately 100% of the total text.

Circuit Packaging Enhancement

      Present design level packaging density allows a plurality
of card assemblies, at a nominal 500 I/O pins per card assembly, to
be positioned within a package but intrinsic to zero insertion force
(ZIF) connectors.  This concept provides the flexibility of design to
allow an increased card assembly count by permitting a plurality of
additional card assemblies to be connected external to the package.
The cards within the assembly (not shown) are maintained in position
by ZIF connectors.

      Referring to Fig. 1, the ZIF connector pins 1 are mounted
through, and soldered to the planar card 3 (Fig. 2) for
interconnection within the package.  By selectively deleting and
otherwise customizing these pins, card assemblies 3 (Fig. 2) may then
be plugged/inserted onto the outside of the planars.

      Another feature of the proposed packaging concept is the use of
pinless headers 5 for cabling; however, customizing for card mounting
to the headers, as shown in the drawing, provides an enhanced
packaging design with the added option of mounting additional card
assemblies as needed.