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Browse Prior Art Database

Level-Sensitive Scan Design in Circuit Emulator

IP.com Disclosure Number: IPCOM000119437D
Original Publication Date: 1991-Jan-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 1 page(s) / 59K

Publishing Venue

IBM

Related People

Bell, R: AUTHOR [+4]

Abstract

This level-sensitive scan design (LSSD) in circuit emulator (ICE) provides test access to internal logic states of chips without special support circuitry at a system level. Thus, hardware problems in very large-scale integrated (VLSI) circuit chips may be diagnosed relatively inexpensively.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 58% of the total text.

Level-Sensitive Scan Design in Circuit Emulator

      This level-sensitive scan design (LSSD) in circuit emulator
(ICE) provides test access to internal logic states of chips without
special support circuitry at a system level.  Thus, hardware problems
in very large-scale integrated (VLSI) circuit chips may be diagnosed
relatively inexpensively.

      Many VLSI circuit chips have LSSD designs to allow random
patterns test coverage.  The LSSD scan strings provide ability to
examine, modify, and restore contents of the VLSI logic and then to
resume system debug.  The design of this ICE allows separating it
from a target system and provides the ICE function via the LSSD
capability built into the VLSI chips.

      During system debug, a chip may be replaced by the ICE socket
with no changes to connections, or other hardware or software and
perform a VLSI function at system speed.  To provide this capability,
the ICE buffers the VLSI module input/output (I/O) with high
performance latches.  This ICE buffering is designed to make the VLSI
I/O delay plus the buffer delay equal to specified I/O delay.  Thus,
outputs from the VLSI module stored in the latches may be used to
drive the ICE socket when the VLSI module is stopped. Scanning can
therefore occur without changing the state of the target system, and
inputs and outputs of a VLSI chip can be monitored.  This feature
allows forcing error conditions and/or overriding erroneous input
from the system.

    ...