Browse Prior Art Database

High Performance Bicmos Sensing Scheme for Static Register Arrays

IP.com Disclosure Number: IPCOM000119452D
Original Publication Date: 1991-Jan-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 1 page(s) / 36K

Publishing Venue

IBM

Related People

Aipperspach, AG: AUTHOR [+2]

Abstract

Described is an improved sensing scheme of a static register array which is illustrated in the figure. Shown is the output portion of the storage latch and the means by which the cell location is selected and its contents propagated to the outputs of the macro.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

High Performance Bicmos Sensing Scheme for Static Register Arrays

      Described is an improved sensing scheme of a static register
array which is illustrated in the figure.  Shown is the output
portion of the storage latch and the means by which the cell location
is selected and its contents propagated to the outputs of the macro.

      The storage cell's output inverter 1,2 has been improved by
replacing the P-channel pullup device with a bipolar NPN pullup.  The
P-channel typically limits pullup performance.  Both phases of the
data are available in a register cell and are able to drive the new
inverter with no additional circuitry.  In multi- port applications,
the NPN can drive all ports with minimal change to performance.

      When the address vector selects a cell, the N-channel passgate
3 drives data on a node common to all locations with the same address
segment.  Devices 4 and 5 are used to limit the voltage swing of this
node.  By limiting the voltage, 1 and 2 of the storage cell are able
to charge and discharge this node faster, thereby improving overall
performance.  Devices 6 through 9 are engineered to sense the reduced
levels of the common node and pass the data to the output drivers of
the macro.

      Disclosed anonymously.