Browse Prior Art Database

Overlapped Execution With Load Multiple And Store Multiple

IP.com Disclosure Number: IPCOM000119564D
Original Publication Date: 1991-Feb-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 85K

Publishing Venue

IBM

Related People

Kahle, JA: AUTHOR

Abstract

This article describes a way to overlap the execution of load multiple or store multiple instructions with other nonstorage operations. Because these instructions can be executed in parallel, the effective cycles per instruction (CPI) can be reduced, thereby increasing the performance of computing system. This invention could be used in any system with load and store multiple instructions, but this article will refer to a reduced instruction set computer (RISC) system with register tag allocation. The instruction set will contain branch, register-to-register operations, and register-to-memory and memory-to-register moves.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Overlapped Execution With Load Multiple And Store Multiple

      This article describes a way to overlap the execution of
load multiple or store multiple instructions with other nonstorage
operations. Because these instructions can be executed in parallel,
the effective cycles per instruction (CPI) can be reduced, thereby
increasing the performance of computing system.  This invention could
be used in any system with load and store multiple instructions, but
this article will refer to a reduced instruction set computer (RISC)
system with register tag allocation.  The instruction set will
contain branch, register-to-register operations, and
register-to-memory and memory-to-register moves.

      There are two basic features that need to be added to the
execution unit to make the overlap of these instructions possible.
First, an incrementer is required to generate the addresses required
for the load multiple and store multiple instructions.  Second, the
register allocation scheme must be modified to allocate a range of
instructions instead of a single register.

      In a typical RISC system, two fields are added together to form
an effective address for a load or store (either two registers are
added together, or an immediate field and a register are added
together). Once this address is generated, a typical RISC system uses
its adder to increment the address.  When an incrementer is added to
the system to perform the sequencing, the adder is then free to
process other register-to-register operations.  A multiplexer (mux)
is also required before the memory control logic to determine if the
address will be generated by the adder or the incrementer.

      RISC systems also use scoreboarding or register tag allocation
to keep track of which registers are invalid (i.e., registers that
are waiting for data from memory.) Register tag allocation works by a
direct comparison of the allocated tag and regist...