Browse Prior Art Database

Computer Microcode Control With First Cycle Hardwired

IP.com Disclosure Number: IPCOM000119581D
Original Publication Date: 1991-Feb-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 160K

Publishing Venue

IBM

Related People

Chang, JH: AUTHOR [+2]

Abstract

A technique is described whereby computer microcode is used to control all data paths with the first cycle operation hardwired. The design takes both structural advantage of microcoded control and the performance advantage of hardwired control.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 43% of the total text.

Computer Microcode Control With First Cycle Hardwired

      A technique is described whereby computer microcode is
used to control all data paths with the first cycle operation
hardwired.  The design takes both structural advantage of microcoded
control and the performance advantage of hardwired control.

      Generally, the use of microcode to control all the data paths
is recognized as a clean organized approach in implementing computer
architecture, such as the complex instruction set computer (CISC),
e.g., IBM System/370 architecture.  However, microcode control
requires an extra step to fetch the microcode (UF) for execution.  To
implement this requires either an extra pipeline stage, e.g., IF-ID-
UF-AG-OF-EX instead of IF-ID-AG-OF-EX, or the cycle time will be
longer if both the ID and UF are executed in one cycle.  An extra
pipeline stage means that an extra cycle is required when the
sequential pipeline is disrupted. Therefore, performance can suffer,
especially when there is no branch prediction hardware incorporated
on a chip.

      The concept described herein removes the performance penalty of
having an extra UF pipeline stage by implementing an address
generation (AGEN) operation.  This will be the first operation of any
instruction which requires accessing storage.  It is designed to be
in hardware and to overlap with the first UF of an instruction.  In
[*], the first UF is also hidden, but a great deal of hardware is in
the instruction preprocessing function (IPPF) which is responsible
for all, not just the first cycle, address computations and operand
fetches of an instruction.  Also, the microcode in 3033 is only used
to control the E-unit.

      In an effort to reduce the hardware design complexity, it has
been decided that all operations, including AGEN, operand fetch and
execution should be under the full control of the microcode.
However, in order to hide the first UF of an instruction, the first
cycle of an instruction should be hardwired.

      The pipeline has five stages: IF-ID-AG-OF-EX.  The IF and ID
are asynchronous to the rest of the pipeline.  That is, the IF will
be initiated by the instruction fetch unit (IFU) as long as the
instruction buffer (IBUF) is not full and the IF is not inhabited by
the instruction decoder (I-ASSEM).  The instruction will be decoded
by the I-ASSEM as long as the next instruction is ready in the IBUF
and the instruction decode output register (IDOR) is not occupied.
The execution pipeline, AG-OF-EX, is non-strict as compared with the
3033, e.g., there is no put-away stage and a simple RR operation can
be completed as early as in the AG.  A selective roll-back is
implemented for handling out-of-order execution.  The reason for
implementing a non-strict pipeline is that, in the absence of branch
prediction hardware and without a lot of pipeline buffers, to
generate results and to set the condition code as early as possible
can shorten the pipeline in...