Browse Prior Art Database

Memory Partition Table for Multiprocessor Optimization

IP.com Disclosure Number: IPCOM000119584D
Original Publication Date: 1991-Feb-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 84K

Publishing Venue

IBM

Related People

Liu, L: AUTHOR

Abstract

Disclosed is techniques for optimizing performance of a multiprocessor system in which the memory may be partitioned. The approach is to employ a memory partition table to record the usage of individual memory partitions by individual processors.

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Memory Partition Table for Multiprocessor Optimization

      Disclosed is techniques for optimizing performance of a
multiprocessor system in which the memory may be partitioned.  The
approach is to employ a memory partition table to record the usage of
individual memory partitions by individual processors.

      In certain computer systems the (main) memory may be
partitioned (e.g., into 1 megabyte partitions).  Each partition may
be dynamically assigned to be used by particular process/system under
certain hypervisor control. Furthermore, in a multiprocessor
environment, a particular underline process/system may be affixed to
run on particular processor(s).  Under this partitioned environment,
the concurrently running systems rarely share memory data.  Data
coherence control is clearly an important factor in multiprocessor
design.  With the partitioned system structure, we may optimize the
performance with the knowledge of specific usage of a memory
partition by particular processors.

      Assume the (main) memory is partitioned into p partitions {Mi
1&i&p} and that there are n processors {Pj 1&j&n}.  We will consider
a partition table (PT), which may be viewed logically as
two-dimensional bit matrix.  The bit PT(i,j) represents the knowledge
of accessibility of partition Mi by processor Pj.  When bit PT(i,j)
is ON (=1), the multiprocessor control will assume that Mi has
recently been accessed by Pj.

      Certain hypervisor-type system control dynamically (but
infrequently) grants and deletes the authorization of data accessing
to particular memory partition(s) by a particular underline process/
system.  Similarly, the system control dynamically (and infrequently)
assigns the set of processor(s) that a particular underline process/
system can run on (which we call the processor affinity).

      We will illustrate the ideas with a particular usage of PT.
Initially, all bits are OFF (=0).  Whenever Mi is accessed by Pj
(e.g., upon a cache miss), the bit PTi,j is turned ON.  Whenever the
authorization of access to Mi by a process/system is deleted, the
hypervisor control will (at prop...