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Browse Prior Art Database

VLSI Chip Factory Test

IP.com Disclosure Number: IPCOM000119608D
Original Publication Date: 1991-Feb-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Badaoui, M: AUTHOR [+4]

Abstract

This article describes a mechanism which allows the factory test of circuits integrated in chips to be performed without any knowledge of the circuits.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 65% of the total text.

VLSI Chip Factory Test

      This article describes a mechanism which allows the
factory test of circuits integrated in chips to be performed without
any knowledge of the circuits.

      This is performed by using the Very Large-Scale Integrated
(VLSI) chip Level-Sensitive Scan Design (LSSD) facilities to provide
the person making the test with a data pattern to be sent at the
chip/card input and with the expected data pattern at chip/card
outputs. This test has no impact at chip/card Shippable Quality Level
and has the same value as a conventional test which implies
disclosure of information on card/chip design and architecture. Only
one extra input, named Factory Test Input, is needed.  When this
input is ON the chip/ card status is Factory Test and Operational
when OFF.

      Factory test structure: As shown in the figure the chip/card
structure is as follows:
      1.   Factory Test Input
           When this input is ON, LSSD Signature Registers
           SSR1 up to SSRN are chained with the chip/card
           signature value.
           This value is always the same for a dedicated
           chip/card and is computed after chip/card Power ON
           Reset (POR) sequence.
           When OFF the device performs normal mode
           operation.
      2.   SERIAL Input
      This input will be used to enter the specific pattern
      provided to...