Browse Prior Art Database

Single Line Interrupt to Microprocessor

IP.com Disclosure Number: IPCOM000119616D
Original Publication Date: 1991-Feb-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 83K

Publishing Venue

IBM

Related People

Karabatsos, C: AUTHOR

Abstract

This programmable hardware apparatus provides an interrupt scheme by which a microprocessor (MPU)-based system can communicate with attached I/O adapters.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Single Line Interrupt to Microprocessor

      This programmable hardware apparatus provides an
interrupt scheme by which a microprocessor (MPU)-based system can
communicate with attached I/O adapters.

      Many microprocessors in popular use have two I/O lines, one
input line to request an interrupt, named INTR, and one output to
acknowledge the interrupt, named INTA.  In the scheme shown in Fig.
1, the INTR line is used as a common line for all adapters A, B...N,
to interrupt the MPU when service is required, and the INTA line is
used to gate the interrupt routine pointer address.

      The pointer address is stored in an 8-bit writable latch (LTCH,
Fig. 2), written by the MPU via an I/O operation.

      Each adapter is attached via this scheme to one interrupt line
INTR through an individual select interrupt lock out (SILO) module
(Figs. 1 and 3).

      When an adapter makes an interrupt request, it places an
interrupt level on line INTR(LUL) to its individual SILO.

      The MPU receives the interrupt via the INTR input line. When
the INTR line is raised high, the MPU, at appropriate times, will
respond with two INTA pulses.  The first pulse will be used by the
logic of Fig. 2 to reset the INTR line and the second pulse will be
used to gate the pointer register LTCH to the data bus.

      Operation of this scheme will be described by way of an
example.
(a)  The pointer register LTCH has been set to some value; let it be
assumed that in this case Pointer = 05.
(b)  All adapters A, B...N have been hard wired to respond...