Browse Prior Art Database

Refresh Control for Dram Sector Buffer

IP.com Disclosure Number: IPCOM000119620D
Original Publication Date: 1991-Feb-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Numata, T: AUTHOR [+3]

Abstract

This article describes a technique to achieve a 'Refresh' control for Dynamic RAM memory used as 'Data buffer' of Hard Disk Sub-System. By applying this technique, Refresh control of Dynamic RAM can be implemented without reducing Data Transfer Speed.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 67% of the total text.

Refresh Control for Dram Sector Buffer

      This article describes a technique to achieve a 'Refresh'
control for Dynamic RAM memory used as 'Data buffer' of Hard Disk
Sub-System.  By applying this technique, Refresh control of Dynamic
RAM can be implemented without reducing Data Transfer Speed.

      This technique can be implemented easily by adding a small
logic circuit in 'Hard Disk Controller', which is a logic circuit
block to handle disk data stream.  The figure shows a simplified
block diagram showing the logic circuit inside the Hard Disk
Controller according to this technique. Block (C) is to generate
cycle signal (E) for DRIVE DATA, which is from a disk, and signal (F)
for HOST DATA, which is from a host system.  Reading from and writing
to memory using 3 signals (J), (K), (L) for host data can be done
only while signal (F) is active.

      On the other hand, reading from and writing to memory for disk
data is done while signal (E) is active.  But in the Hard Disk
system, there are several signals written into disk other than data,
like ID signal for sector identification and servo signal for head
positioning.  On the area for these signals, data does not come from
the disk; therefore, reading from and writing to memory is not
required.

      In this technique, a refresh cycle for memory is inserted in
this drive cycle while memory reading and writing is not required.
To generate this cycle, block (B) generate signal (D) to indicate
data...