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Gate Delay Compensation Technique for Video Dot Stretch Circuit

IP.com Disclosure Number: IPCOM000119622D
Original Publication Date: 1991-Feb-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Iida, H: AUTHOR [+2]

Abstract

Disclosed is a gate delay compensation circuit for a video dot stretch circuit. This circuit detects the variation of the propagation delay of LSI which is caused during a semiconductor manufacturing process. Based on this delay value, dot stretch value (length of the delay stage) is adjusted and dot width on the screen is kept constant irrespective of the LSI variation.

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Gate Delay Compensation Technique for Video Dot Stretch Circuit

      Disclosed is a gate delay compensation circuit for a
video dot stretch circuit.  This circuit detects the variation of the
propagation delay of LSI which is caused during a semiconductor
manufacturing process.  Based on this delay value, dot stretch value
(length of the delay stage) is adjusted and dot width on the screen
is kept constant irrespective of the LSI variation.

      One of the major problems in video dot stretch circuit using
gate delay (Fig. 1) is the variation of the propagation delay time.
If constant dot stretch value is assumed, the appearance of the
character would be different in accordance with LSI differences.

      The circuit shown in Fig. 2 is designed to measure the LSI
delay factor and generates gate delay selection signal for dot
stretch compensation.  The signal (3) is the result of accumulated
delays through delay circuit and the variation of the pulse width of
signal (3) repre sents the variation of LSI chip delay.  Counter
driven by reference clock and decoder circuit converts the delay
variation into the selection signal which selects the compensated dot
stretch value.

      For example,
                               counter        compensated
                                count         dot stretch
                              (measured)   ...