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Reference Circuit for SRAM With Battery Back-Up Capability

IP.com Disclosure Number: IPCOM000119643D
Original Publication Date: 1991-Feb-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 81K

Publishing Venue

IBM

Related People

Akrout, C: AUTHOR [+5]

Abstract

One of the characteristics of a low-power high-speed SRAM architecture consists of switching bitline loads, with an appropriate reference as shown in Fig. 1.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Reference Circuit for SRAM With Battery Back-Up Capability

      One of the characteristics of a low-power high-speed SRAM
architecture consists of switching bitline loads, with an appropriate
reference as shown in Fig. 1.

      When the cell is not selected, the restore devices TR0, TR1,
TR2 are turned on, the bitlines are equalized and restored to the
common mode level. This level is defined by the reference circuit.
Since a cell is selected, TR0, TR1, TR2 are turned off. Then a
differential voltage propagates along the bitlines from the cell to
the sense amplifier.

      The appropriate bitline common mode level is a key parameter
for the following reasons:
  It ensures the cell stability during transient time.
  It shifts the sense amp input signal into a high gain
  region. This yields a better performance.
  As the bitline level is lower, power consumption is
  reduced.

      The reference circuit shown in Fig. 1 could meet the above
criteria.  However, it cannot be applied in a large array.  Since the
overall bitline capacitance increases, the AC restore current
increases, then large devices are needed to build the reference
circuit, so as the DC power consumption becomes prohibitive.

      The present invention relates to a new reference circuit, which
has acceptable active DC current, and VERY LOW standby current. The
DC current is reduced to a few micro-amps when the power supply drops
under 3 volts. Therefore, this circuit can be used in a SRAM which
provides battery back-up capability.
      The schematic is shown in Fig. 2.

      This reference circuit can provide enormous current in order to
restore the bitline level from...