Browse Prior Art Database

Dense SRAM Cell Structure for 16 Mb SRAM Chip And Beyond

IP.com Disclosure Number: IPCOM000119654D
Original Publication Date: 1991-Feb-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 100K

Publishing Venue

IBM

Related People

Hwang, W: AUTHOR [+2]

Abstract

Disclosed is a new vertical SRAM cell structure suitable for the 16 Mb SRAM chip and beyond. It is a four-transistor cell and uses oxygen-doped polysilicon as the load resistor. The cell area is about 48 lithography squares. A schematic vertical cross section and top view of the proposed new cell are shown in Figs. 1 and 2, respectively. A p-substrate and n-channel devices are assumed. Vertical transistors T1, T2, T3 and T4 form the four transistors of the cell, shown in the inset of Fig. 2. The diffusion near the top of the trench between the two trenches also serves as the ground. Oxygen-doped polysilicon is used as the load resistor and is between the metal 1 (connects to the bottom of the trench) and metal 2 (VDD power supply).

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Dense SRAM Cell Structure for 16 Mb SRAM Chip And Beyond

      Disclosed is a new vertical SRAM cell structure suitable
for the 16 Mb SRAM chip and beyond.  It is a four-transistor cell and
uses oxygen-doped polysilicon as the load resistor.  The cell area is
about 48 lithography squares.  A schematic vertical cross section and
top view of the proposed new cell are shown in Figs. 1 and 2,
respectively. A p-substrate and n-channel devices are assumed.
Vertical transistors T1, T2, T3 and T4 form the four transistors of
the cell, shown in the inset of Fig. 2.  The diffusion near the top
of the trench between the two trenches also serves as the ground.
Oxygen-doped polysilicon is used as the load resistor and is between
the metal 1 (connects to the bottom of the trench) and metal 2 (VDD
power supply).  The bitlines are formed by metal 1 (M1) and run
perpendicular to the metal 2 (M2) power lines.  The trenches are
partially filled with n-doped poly.  M1 is utilized to make the
cross-coupling connections of the storage latch.  A self-aligned
contact process is used to make contact with the source/ drain and
the bitline.

      The fabrication procedures of the vertical SRAM cell are
described in the following:

      (1) A low_resistivity P-substrate is used.  The n+ diffusion
wiring lines for BL, BL, and GND about 0.3 mm - 0.5 mm deep are
formed by I/I using the first mask.  LOCOS isolation is formed in the
array and the peripherals, using the second mask.   The device
trenches are etched in the array using a lithographically patterned
Si3N4 mask to a depth of about 2 mm.

      (2) After the trenches are etched, 10 nm gate oxide is formed,
followed by deposition of conformal gate poly (poly I) and 50 nm CVD
oxide deposition.  The gate poly i...