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Large Vds Data Retention Test Pattern for Drams

IP.com Disclosure Number: IPCOM000119662D
Original Publication Date: 1991-Feb-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 80K

Publishing Venue

IBM

Related People

Dhong, SH: AUTHOR [+3]

Abstract

Disclosed is a new data-retention test pattern which holds the bitlines of a DRAM in their latched states, thereby specifically stressing the cell access transistors at their worst-case drain-to-source voltage (Vds).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Large Vds Data Retention Test Pattern for Drams

      Disclosed is a new data-retention test pattern which
holds the bitlines of a DRAM in their latched states, thereby
specifically stressing the cell access transistors at their
worst-case drain-to-source voltage (Vds).

      There are typically two types of test patterns for testing for
data retention.  One method is where a regular test pattern, such as
MARCH or Unique Address Test, is run and the cells are refreshed at
the specified interval.  A second method is where the chip is written
with a background pattern, allowed to pause for some interval, and
then read back.  However, in both of these methods, the bitlines are
in their equalized state for most of the time and do not spend long
enough intervals of time in their latched state to bring out
data-retention fails due to the sub-threshold source-drain leakage
through the cell access transistor, as shown in the figure.  The new
test pattern tests the data retention with the worst-case
drain-to-source voltage applied across the cell access transistor and
can detect fails due to sub-threshold source-drain leakage that would
go undetected with conventional test patterns.

      The new test pattern starts with first writing all physical
zeros i.e., discharged capacitors.  The background is written
rippling x in order not to violate the refresh requirement.  Next,
one wordline is selected in an active block under test by making RAS
fall, but holding CAS up. This results in one active wordline and all
the sense amplifiers and bitlines in a latched state.  RAS and CAS
are held in this state for a period substantially longer than a
normal RAS cycle or page-mode cycle.  At the end of this long
RAS-only cycle, a burst refresh cycle is executed so as not to
violate the retention interval of the chip.  This long RAS-only cycl...