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Gate Drive Scheme for Thin Film Transistor/Liquid Crystal Displays

IP.com Disclosure Number: IPCOM000119668D
Original Publication Date: 1991-Feb-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Depp, SW: AUTHOR

Abstract

Disclosed is a driving method for thin film transistor liquid crystal displays (TFT/LCDs) which reduces the effect of gate line delay by appropriately shaping the gate drive pulse. Gate delay affects TFT/LCDs by lowering and delaying effective gate voltage for transistors far from the driver side of the display which results in grayscale errors and image artifacts.

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Gate Drive Scheme for Thin Film Transistor/Liquid Crystal Displays

      Disclosed is a driving method for thin film transistor
liquid crystal displays (TFT/LCDs) which reduces the effect of gate
line delay by appropriately shaping the gate drive pulse.  Gate delay
affects TFT/LCDs by lowering and delaying effective gate voltage for
transistors far from the driver side of the display which results in
grayscale errors and image artifacts.

      A new gate drive pulse is shown in the figure which reduces
these problems.  The gate pulse starts prior to the actual line time
when the appropriate data voltages are on the address lines.  This
causes only a small error in the rms voltage applied to the liquid
crystal but greatly increases the source-drain conductance of the
transistors at the undriven end of the gate line (where gate delay is
most significant) at the critical time when the appropriate data
voltages appear.  Prior to the end of the line time, the gate pulse
goes negative, abruptly shutting off the transistor before the next
set of data voltages appear.

      The advantage of this gate drive scheme is an improvement in
effective gate delay by approximately a factor of two.  There is no
change in panel materials, devices or structure and only a moderate
increase in gate driver complexity.