Browse Prior Art Database

Interrupt Controller for a Microprocessor System

IP.com Disclosure Number: IPCOM000119669D
Original Publication Date: 1991-Feb-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 5 page(s) / 184K

Publishing Venue

IBM

Related People

Cockburn, GJ: AUTHOR [+3]

Abstract

An interrupt controller in a microprocessor system has the priority of different tasks assigned to registers. The priority of each task is dynamically variable and may be altered during execution. An embodiment is described in which features of such an interrupt controller enable a system interrupt to be implemented efficiently with the minimum of software overhead. Task priorities are not fixed by the interrupt controller hardware. In different applications, the same task level may use a different interrupt priority. If a task wishes to perform some lengthy processing it may lower its priority so that it does not hold off more important processing in the other tasks. A Sleep mode allows a task to wait a short time while making the processor available for use by other tasks.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 36% of the total text.

Interrupt Controller for a Microprocessor System

      An interrupt controller in a microprocessor system has
the priority of different tasks assigned to registers.  The priority
of each task is dynamically variable and may be altered during
execution.  An embodiment is described in which features of such an
interrupt controller enable a system interrupt to be implemented
efficiently with the minimum of software overhead.  Task priorities
are not fixed by the interrupt controller hardware.  In different
applications, the same task level may use a different interrupt
priority.  If a task wishes to perform some lengthy processing it may
lower its priority so that it does not hold off more important
processing in the other tasks. A Sleep mode allows a task to wait a
short time while making the processor available for use by other
tasks.

      A microprocessor which uses this interrupt controller provides
eight levels for executing code.  Each level has a separate Program
Status Word that contains the program counter.  When an interrupt is
taken, the microprocessor first saves the PSW for the current level
and then loads a PSW for the new level which can begin executing.
The microprocessor provides the following signals for interrupt
control:
*    'CUR INTRPT LEVEL OUT' a 3-bit bus that indicates which level is
currently processing.
*    'INTERRUPT REQUEST' an input that requests to swap levels.
*    'INTERRUPT LEVEL IN' a 3-bit bus that specifies the new level.
*    'PSW SWAP OUT' indicates that 'INTERRUPT REQUEST' has been
honored and that a PSW swap is taking place.
*    'INTRPT RESPONSE OUT' indicates a completed PSW swap and that
'INTERRUPT LEVEL IN' can be changed.

      Levels are numbered 0 - 7, but this does not imply any priority
scheme;  it will switch from any level to any other level when
instructed by 'INTERRUPT REQUEST' and 'INTERRUPT LEVEL IN'.  The
eight levels equate to tasks that can be activated without the need
to save and restore registers.

      The interrupt controller is designed to allow the priority of
each level to be assigned in a register.  The same hardware can be
used in different applications where the priority requirements are
different.  Priorities are not hard-wired and tasks may raise or
lower their priority during execution if required.  Execution
priority is never raised erroneously if an interrupt arrived during
low priority processing.  Each task is made eligible to run by
interrupts.  Priorities of each eligible level are used to select
which level will run.  Levels with the smallest priority number
("Highest priority") will be chosen to execute.  If several levels
are eligible at the highest priority, and one of them is already
running, it continues to run.  If several levels become eligible at
the highest priority, and none are running, then the lowest level
number is chosen.  In the absence of any eligible task, level 7 will
execute.

      Each...