Browse Prior Art Database

Buffer Address Checking for an Input/Output Processor

IP.com Disclosure Number: IPCOM000119680D
Original Publication Date: 1991-Feb-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 4 page(s) / 105K

Publishing Venue

IBM

Related People

Cleveland, LD: AUTHOR [+3]

Abstract

A real-time method of checking data buffer address and control signals.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Buffer Address Checking for an Input/Output Processor

      A real-time method of checking data buffer address and
control signals.

      In a direct access storage device (DASD) subsystem it is often
necessary to use a SRAM or DRAM for data buffering to match system
and DASD data transfer rates.  It is absolutely imperative that data
integrity be preserved when it passes through the buffer.  Usually,
the data path has parity checking as a minimum safeguard.  When using
DRAM, an error-correcting code (ECC) is often used.  No such steps
are generally taken with respect to the buffer address lines or
control signals, such as chip select and write enable. This leaves a
gap in data integrity protection as data moves to and from the RAM
buffer.  A test is usually performed at power on to detect stuck
address bits; however, in today's operating environments, systems are
rarely powered down.

      Since any scheme to add checking on data buffer address signals
requires additional hardware, it is important that the desired end
can be accomplished in a variety of ways. Disclosed offers a number
of approaches to essentially the same end.  An assumption is made
that the address lines originate from a VLSI chip.

      Fig. 1 shows how address lines can be checked if the
originating VLSI module has sufficient spare I/O pins.  The address
lines are wrapped back into the chip and a direct compare is made
with the signals that were driven.  Control signals, such as Chip
Selects and Write Enable, can also be wrapped and checked.  At the
card level this requires additional care in wiring since the wrap
back path must first encounter the actual buffer RAM pin before being
routed to the originating VLSI chips inputs.  This ensures that the
complete physical signal path to the buffer RAM and back to the VLSI
chip is included in the check.  This will generally add extra wiring
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