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Floating Point Exception Handling (Denormalization)

IP.com Disclosure Number: IPCOM000119682D
Original Publication Date: 1991-Feb-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 4 page(s) / 125K

Publishing Venue

IBM

Related People

Goldberg, WD: AUTHOR [+4]

Abstract

A technique is described for the efficient handling of masked exponent overflow exception conditions in a binary floating point processor system. The technique utilizes an algorithm for denormalizing floating point arithmetic results while conforming to the requirements of IEEE Standard 754 for binary floating point arithmetic. The algorithm uses the concept of denormalizing operands and routing the operands through existing data flow to minimize the required logic and the impact on performance.

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This is the abbreviated version, containing approximately 51% of the total text.

Floating Point Exception Handling (Denormalization)

      A technique is described for the efficient handling of
masked exponent overflow exception conditions in a binary floating
point processor system.  The technique utilizes an algorithm for
denormalizing floating point arithmetic results while conforming to
the requirements of IEEE Standard 754 for binary floating point
arithmetic.  The algorithm uses the concept of denormalizing operands
and routing the operands through existing data flow to minimize the
required logic and the impact on performance.

      Exponent underflow in floating point architecture occurs
whenever the exponent falls below the minimum value of the target
format, referred to as exponent minimum (Emin).  The IEEE Standard
754 allows for a mask bit in a floating point status word register to
indicate how exponent underflows are to be handled, either mask (trap
disabled) or unmasked (trap enabled).  Since the concept is concerned
only with masked exponent underflows, the requirement is such that
the fraction be denormalized (right shifted) to the point that brings
the exponent into the range of the destination format.  The algorithm
described herein centers on the handling and reporting of masked
exponent underflows in a floating point processor implementing the
IEEE Standard 754.  Therefore, this special condition utilizes the
following seven floating point functional units:
   1.  Control function (CTL) - Provides the controls to properly
sequence the execution of all operations.
     2.  Floating Point Registers (FPRs) - Contains an array of
registers which provide temporary storage of operands and the results
of the computation.  Also, the registers contain "unpack" and "pack"
logic for converting operands from their stored precision into a
common working format and from the common working format into the
target precision.
     3.  Exponent Function (EXP) - Contains logic to perform all
exponent handling.  Also, contains a copy of the upper seventeen bits
of the FPRs.
     4.  Add function (ADD) - Contains a sixty-seven-bit right
shifter which is used for fraction alignment and a sixty-seven-bit
multi-function adder.
     5.  Multiply Function (MUL) - Contains logic to multiply two
sixty-four-bit functions.
     6.  Divide Function (DIV) - a) Contains logic to divide one
sixty-four-bit fraction by another,  b) Contains logic to drive the
partial remainder resulting from dividing one sixty-four-bit fraction
by another, and c) Contains logic to compute the square root of a
sixty-four-bit fraction.
   7.  Normalize Function (NOR) - Contains a sixty-four-bit left
shifter used for normalization and also contains a sixty-four- bit
rounder.

      The ADD functional unit contains a right shifter and the NOR
functional unit contains a left shifter.  This concept was
implemented in place of using a left-right shifter, or barrel
shifter, which is normally used to perform...