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Mini-Trenches in Polysilicon for DRAM Storage Capacitance Enhancement

IP.com Disclosure Number: IPCOM000119713D
Original Publication Date: 1991-Feb-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 75K

Publishing Venue

IBM

Related People

Oehrlein, GS: AUTHOR [+2]

Abstract

A technique is described whereby the area of a capacitor suitable for DRAM storage can be increased. This is achieved by introducing many mini-trenches in a polysilicon layer without lithography, thereby increasing the area provided for a capacitor between two polysilicon electrodes, often referred to in the literature as a stacked capacitor.

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Mini-Trenches in Polysilicon for DRAM Storage Capacitance Enhancement

      A technique is described whereby the area of a capacitor
suitable for DRAM storage can be increased. This is achieved by
introducing many mini-trenches in a polysilicon layer without
lithography, thereby increasing the area provided for a capacitor
between two polysilicon electrodes, often referred to in the
literature as a stacked capacitor.

      The principle of the idea is illustrated in Fig. 1. A
polysilicon film is shown into which a random array of trenches has
been etched by RIE with an average diameter smaller than the film
thickness and with close spacing. This procedure is designed to
increase the surface area provided for a capacitor. The polysilicon
surface is then covered with the standard thin dielectric and with a
top polysilicon layer acting as the counter electrode.

      The method of producing the mini-trenches relies on non-uniform
masking of the polysilicon during RIE. The masking should be provided
without lithography and be such that on average the hole diameters
and distribution are uniform and well controlled. One way to achieve
this is to use the non-uniformities inherent in a thin oxide film,
either native or grown. It is known that Cl- and Br-based reactive
ion etching processes can exhibit extremely high selectivity in
etching silicon vs.  silicon dioxide. In conventional Si trench
etching this high etch selectivity necessitates rigorous removal of
the native oxide prior to starting the Si trench etching process. It
is proposed here to use incomple...