Browse Prior Art Database

Noise Reduction in VLSI Chips

IP.com Disclosure Number: IPCOM000119723D
Original Publication Date: 1991-Feb-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Klink, E: AUTHOR [+2]

Abstract

On VLSI chips, electrical noise generated by simultaneously clocking all shift register latches (SRLs) may lead to reduced performance and/or logic malfunction within the chips.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 72% of the total text.

Noise Reduction in VLSI Chips

      On VLSI chips, electrical noise generated by
simultaneously clocking all shift register latches (SRLs) may lead to
reduced performance and/or logic malfunction within the chips.

      Presently, up to 13,000 SRLs are implemented on one chip.
During shift operations, such as LSSD shifting during a test and in
the system environment, all SRLs are switched simultaneously.  This
leads to excessive chip noise.

      A methodology is disclosed to reduce such noise by staggering
the shift clock.

      The SRL set consists of one subset (group I) forming part of
the functional chip logic and one or more subsets (group II) forming
part of memory array macros (shiftable array cells).  The second
group (group II) is used in the shift mode only.  The idea of the
proposed concept is to delay the shift clocks for group II (Fig. 1).
This delay between group I and group II prevents a superposition of
noise of the two groups, which leads to much lower noise amplitudes
that do not affect the functionality of the chips.

      As shown in Fig. 1, shifting is performed at half the system
clock rate.  The time between two active shift clocks is about half
the cycle time.  Any delay of the shift clock for group II which is
less than 1/4 of the cycle time will not cause overlapping A- and
B-clocks despite clock skews.

      Owing to the different application modes of the SRLs, the shift
clocks (A- and B-clocks) have to meet diff...