Browse Prior Art Database

Off-Level Interrupt Handling

IP.com Disclosure Number: IPCOM000119727D
Original Publication Date: 1991-Feb-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 77K

Publishing Venue

IBM

Related People

Kampe, MA: AUTHOR [+4]

Abstract

A program is disclosed that provides a mechanism where the processing of long hardware and timer interrupt service routines do not adversely affect the overall system integrity and the integrity of other I/O devices. This is accomplished by splitting the interrupt service routine into two pieces, one short piece running at the high priority of the interrupt and the bulk of the interrupt service routine is run at a lower priority, at a later time. This off-level processing allows other I/O devices a chance to process their interrupts in a timely fashion.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Off-Level Interrupt Handling

      A program is disclosed that provides a mechanism where
the processing of long hardware and timer interrupt service routines
do not adversely affect the overall system integrity and the
integrity of other I/O devices. This is accomplished by splitting the
interrupt service routine into two pieces, one short piece running at
the high priority of the interrupt and the bulk of the interrupt
service routine is run at a lower priority, at a later time.  This
off-level processing allows other I/O devices a chance to process
their interrupts in a timely fashion.

      Computing devices are generally composed of a processor or
micro- processor, memory and some input/output (I/O) devices.  These
I/O devices in a normal running sequence need to be serviced by the
processor on a somewhat regular basis.  These I/O devices need
service based on an external stimulus, on a timed basis, or on the
normal sequence of the resident application.  In the case of an
external stimulus and timed basis, requests for service are generally
referred to as interrupts to the processor.

      The solution is to split long interrupt routines into a high
priority part that performs very little processing, and a lower
priority off-level part that can safely execute for a much longer
time without interfering with high priority tasks.

      Since there is generally a significant time delay between the
time the off-level process is asked to wake up and the time the
off-level process actually finishes the service routine,  other
interrupts could have arrived.  So part of the off-level process is
to provide a queue where the information about multiple interrupts
are stored...