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Interleaved Two-Port First-In, First-Out Random-Access Memory

IP.com Disclosure Number: IPCOM000119742D
Original Publication Date: 1991-Feb-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 53K

Publishing Venue

IBM

Related People

Braceras, GM: AUTHOR [+2]

Abstract

By creating two quite independent memory array halves comprised of arrays of single port static random-access memory (SRAM) cells and addressing the two halves alternately in first-in, first-out (FIFO) sequence, simultaneous read and write, or two-port mode of operation becomes possible. Thus, significant performance improvement is realized in FIFO memory without having a penalty of additional semiconductor area for extra transfer devices, bit lines, and wordline normally required in construction of a two-port cell array.

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Interleaved Two-Port First-In, First-Out Random-Access Memory

      By creating two quite independent memory array halves comprised
of arrays of single port static random-access memory (SRAM) cells and
addressing the two halves alternately in first-in, first-out (FIFO)
sequence, simultaneous read and write, or two-port mode of operation
becomes possible.  Thus, significant performance improvement is
realized in FIFO memory without having a penalty of additional
semiconductor area for extra transfer devices, bit lines, and
wordline normally required in construction of a two-port cell array.

      Use is made of the FIFO requirement that RAM addressing is
always sequential for both read and write functions.  The RAM is
divided into ODD and EVEN segments such that each successive read and
write takes place in opposite sides of the RAM.  As shown in the
figure, the ODD 2 and EVEN 2 array segments are physically separated
and have separate word and bit decoders 4 and 6.  Thus, two unique
RAM accesses, one to the ODD and one to the EVEN, are allowed during
one system clock cycle.  In write-only operation, write address
counter 8 writes data into the EVEN half first and then into the ODD
half and continues in this FIFO fashion until either the write signal
ends or the read signal becomes active.  In read-only operation, read
address counter 10 causes similar addressing and FIFO operation.

      In two-port mode of operation, when the read address is ODD and
the...