Browse Prior Art Database

Enhanced Observability of Daisy-Chained Chips on Multi-Chip Modules

IP.com Disclosure Number: IPCOM000119745D
Original Publication Date: 1991-Feb-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 42K

Publishing Venue

IBM

Related People

Altmann, WC: AUTHOR

Abstract

By adding gating circuitry to one logic chip on a module and allowing each chip's scan chain to be accessed independent of functionality of chains on other chips, test access is provided to all chips while keeping module pin requirements low.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 91% of the total text.

Enhanced Observability of Daisy-Chained Chips on Multi-Chip Modules

      By adding gating circuitry to one logic chip on a module and
allowing each chip's scan chain to be accessed independent of
functionality of chains on other chips, test access is provided to
all chips while keeping module pin requirements low.

      The figure is a diagram  of logic to be added to at least ne
logic chip of a daisy-chained module of chips.  In this example, six
module input/output (I/O) pins to address four SELECT lines, one
scan-in si, and one scan-out so lines are required to select and
access chains of up to 15 chained chips.  Three chips X, Y, and Z are
selected as follows: for chip X, gates 1, 2, B, and C are enabled;
for chip Y, gates A, 3, 4, and C are enabled; for chip Z, gates
A, B, 5, and 6 are enabled.  To serially access all three chips X, Y,
Z, gates 1, 2, 3, 4, and 5 are enabled.  This approach can be
extended to provide access for individual testing of any number of
chained chips.

      To maintain earlier test strategy at higher packaging levels,
chained chips can be chained together serially by default.  The
SELECT inputs can be wired HIGH or LOW by pulling them to a fixed
level on the logic when they are unconnected at the card level.
However, the SELECT lines need not be unconnected at the card level
and card tests can access chips individually if the logic is added to
the control on the card.

      Thus, specific identification of all rework...