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Current Switch Circuit with Programmable Speed-Up Capacitor

IP.com Disclosure Number: IPCOM000119756D
Original Publication Date: 1991-Feb-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 42K

Publishing Venue

IBM

Related People

Barish, A: AUTHOR [+4]

Abstract

A programmable speed-up capacitor structure is proposed to be connected or not connected to the common emitter of a current switch circuit in accordance with a specific design need. For NOR gate operation (out of phase), this capacitor shall be so connected to enhance the performance of the NOR gate. For OR gate operation (in phase), this capacitor shall be off to avoid degrading its performance. This capacitor "on" and "off" operation is automatically controlled under the circuit book design wiring rule.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 94% of the total text.

Current Switch Circuit with Programmable Speed-Up Capacitor

      A programmable speed-up capacitor structure is proposed to be
connected or not connected to the common emitter of a current switch
circuit in accordance with a specific design need.  For NOR gate
operation (out of phase), this capacitor shall be so connected to
enhance the performance of the NOR gate.  For OR gate operation (in
phase), this capacitor shall be off to avoid degrading its
performance.  This capacitor "on" and "off" operation is
automatically controlled under the circuit book design wiring rule.

      A typical current switch circuit is as shown in Fig. 1. The
connection of the speed-up capacitor at the common emitter (CSC)
shall greatly enhance the NOR gate operation of the current switch.
However, for OR gate operation, this capacitor connection shall
degrade its performance.  This drawback of using the speed-up
capacitor is now removed by specifying the wiring rule of the book
design so that the connection can only take place for NOR gate.

      The specific speed-up capacitor structure in the order of .1pf
to .2pf can be conveniently implemented under the wiring channel of
the silicon area such as that shown in Fig. 2 of a circuit cell.

      In summary, (1) a speed-up capacitor is conveniently built in a
current switch circuit cell to enhance NOR gate performance; and (2)
the connection of this capacitor to a current switch operation is
under an EDS wiring program cont...