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Browse Prior Art Database

Clamped Output Scaled BICMOS Circuits

IP.com Disclosure Number: IPCOM000119763D
Original Publication Date: 1991-Feb-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 52K

Publishing Venue

IBM

Related People

Puri, YK: AUTHOR [+2]

Abstract

Scaling of VLSI device and circuit dimensions tends to make the performance of BICMOS logic circuits less attractive because the circuits must operate from reduced power supply voltages. Attempts to improve performance have generated other problems, one of them being that the circuit output at steady-state is sensitive to noise coupled into the output line, which can cause over-stressing of some MOS devices.

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This is the abbreviated version, containing approximately 73% of the total text.

Clamped Output Scaled BICMOS Circuits

      Scaling of VLSI device and circuit dimensions tends to make the
performance of BICMOS logic circuits less attractive because the
circuits must operate from reduced power supply voltages.  Attempts
to improve performance have generated other problems, one of them
being that the circuit output at steady-state is sensitive to noise
coupled into the output line, which can cause over-stressing of some
MOS devices.

      The circuit shown in the figure is designed to work with lower
power supply levels and it is insensitive to noise coupled from the
output line.  A representative two-input NAND circuit is shown, but
the technique is directly applicable to most common logic circuit
functions. Diode-connected bipolar transistor Q0 raises the FET
sources by VBE so as to limit their voltage stresses to VDD-VBE. The
standard output down level is VBE instead of ground, and the output
up level is VDD-VBE.  Circuit performance is improved over
conventional designs because the drive level is increased.

      Bipolar device Q3 acts as a clamp to prevent the output from
being driven negatively into a high impedance condition in the down
level state.  Such excursions would otherwise over-stress some of the
FET devices for long periods of time under certain operational
conditions.  Likewise, bipolar device Q4 clamps the output to VDD-VBE
in the output up-level state when noise would otherwise act to drive
the circuit upward into a...