Browse Prior Art Database

High Speed Address Stacking for Processors and Finite State Machines

IP.com Disclosure Number: IPCOM000119770D
Original Publication Date: 1991-Feb-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 41K

Publishing Venue

IBM

Related People

Barker, K: AUTHOR [+3]

Abstract

Disclosed is a technique for stacking subroutine Return Addresses and retrieving them. The method allows the stacking to take place in a single instruction cycle of the associated processor or finite state machine.

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This is the abbreviated version, containing approximately 100% of the total text.

High Speed Address Stacking for Processors and Finite State Machines

      Disclosed is a technique for stacking subroutine Return
Addresses and retrieving them.  The method allows the stacking to
take place in a single instruction cycle of the associated processor
or finite state machine.

      The key feature of this design is the shifted pattern produced
by the Stack Address Counter, see Fig. 1.  The stack output
multiplexor address which selects the stack element is shifted with
respect to the REG address used to put addresses on the stack.  This
shift allows a single counter to address both the next stack entry
element and the last entered element at the same time.

      The Up-Down counter is always pointing to the next available
register for any stacking operation.  If push is active, then one of
the registers will be loaded.  At the same time, the Counter is
pointing at the register which was loaded last.  This double use of
the counter is possible due to the shifted pattern between the MUX
and the Reg array.

      With sequential or repeated Push operations, the Counter is
incremented as addresses are added to the Stack. Similarly, repeated
Pull operations retrieve stacked information as the counter steps
down.  The Counter output always points to the next register for Push
operations and the last updated register for Pull operations.

      Disclosed anonymously.