Browse Prior Art Database

Improved Debug for Pipelined Processors

IP.com Disclosure Number: IPCOM000119775D
Original Publication Date: 1991-Feb-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 35K

Publishing Venue

IBM

Related People

Slane, AA: AUTHOR

Abstract

Today's processors are usually pipelined to increase performance. However, pipelined processors cause many headaches for debuggers. This is because there are several instructions executing in the pipeline at any given time. To improve the usability of a pipelined processor, a debug mode can be added that allows only a single instruction to execute in the pipeline at any given time.

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Improved Debug for Pipelined Processors

      Today's processors are usually pipelined to increase
performance.  However, pipelined processors cause many headaches for
debuggers.  This is because there are several instructions executing
in the pipeline at any given time. To improve the usability of a
pipelined processor, a debug mode can be added that allows only a
single instruction to execute in the pipeline at any given time.

      A solution to this problem is to provide a processor mode that
can be turned on and off that changes the pipeline instruction start
logic.  Figs. 1 and 2 illustrate a simple instruction pipeline, and
how instructions will flow through the pipeline when the new debug
mode is inactive.

      Fig. 3 illustrates how instructions will flow through the
pipeline when the new debug mode is active.  The empty stages in the
diagram represent idle stages of the pipeline. A new instruction will
not start executing until the previous instruction completes
executing.

      Disclosed anonymously.