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IEEE Floating Point Divider Reciprocal Seed Through Linear Approximation

IP.com Disclosure Number: IPCOM000119777D
Original Publication Date: 1991-Feb-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 60K

Publishing Venue

IBM

Related People

Faget, RR: AUTHOR [+3]

Abstract

Disclosed is a method to generate a reciprocal seed for the divisor(X) which can lead to faster quotient determination for floating point division in a hardware Floating Point Unit (FPU).

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IEEE Floating Point Divider Reciprocal Seed Through Linear Approximation

      Disclosed is a method to generate a reciprocal seed for the
divisor(X) which can lead to faster quotient determination for
floating point division in a hardware Floating Point Unit (FPU).

      The invention disclosed is a method to generate a reciprocal
seed for the divisor(X) which can lead to faster quotient
determination for floating point division in a hardware FPU.  The
method involves generating a reciprocal seed(Y) by linear
approximation; estimating Y=1/X with line segments within the range
of interest, from X=1 to X=2(the divisor is assumed to be normalized
1.00).  A straight line approximating 1/X, or a portion of the 1/X
curve, in the region from X=1 to X=2, will have as its equation Yappr
= MX + B.  It can be seen that Yappr can be generated with a
single multiply/add as soon as the slope(M) and the Y intercept(B)
can be determined.  Multiple lines can be drawn to cover the range
from X=1 to X=2 to provide a more accurate estimate for the
reciprocal.  The actual line which will provide the initial
reciprocal estimate will be selected by analyzing the leading bits of
the divisor, X. As the number of lines increases, so does the
accuracy of the initial reciprocal; however, the number of M and B
values(constants) to be selected from also increases, as well as the
number of divisor bits that have to be analyzed. For a given divisor
range, it is desirable to minimize the act...