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Method of Testing Chips and Joining Chips to Substrates

IP.com Disclosure Number: IPCOM000119785D
Original Publication Date: 1991-Feb-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 50K

Publishing Venue

IBM

Related People

Doany, FE: AUTHOR [+6]

Abstract

Because of thermal expansion mismatch, the C4 solder pad footprint is limited in size, and a high lead contact, high melting point solder must be used to ensure sufficient ductility in the C4 joints and sufficient creep resistance that pressure on the chip for cooling does not cause the C4 joints to flow. We propose using an elastomeric polymer 2 spread on the semiconductor wafer 1 with imbedded wires 3 to make contact to C4 pads 4 for testing. The wafer can be pressed so that the wires make contact with a test bed 5 as in Figure 1.

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Method of Testing Chips and Joining Chips to Substrates

      Because of thermal expansion mismatch, the C4 solder pad
footprint is limited in size, and a high lead contact, high melting
point solder must be used to ensure sufficient ductility in the C4
joints and sufficient creep resistance that pressure on the chip for
cooling does not cause the C4 joints to flow.  We propose using an
elastomeric polymer 2 spread on the semiconductor wafer 1 with
imbedded wires 3 to make contact to C4 pads 4 for testing.  The wafer
can be pressed so that the wires make contact with a test bed 5 as
in Figure 1.

      The wafer is coated with approximately 250 microns of siloxane
elastomer with a polymerizing agent to promote curing.  After the
polymer is cured, an excimer laser at 248 nm wavelength is used to
open holes in the polymer down to the contact pads.  The holes are
then filled with copper 3 by electroplating up from the metal contact
pads 4 at the bottom of the hole.  Our original experiments showed
that a standard pH12 electroless Cu solution did not attack the
siloxane.  We also have shown that Au acts as a catalyst for
electroless Cu solution and did not attack the siloxane.

      After each die and connected wire on the wafer 1 have been
tested on the wafer, the wafer can be diced up in the normal way into
chips 6 and the wires 3 joined to a ceramic, thin film or any other
chip carrier 6 by low temperature solder 7 (i.e., eutectic Pb-Sn) or
intermetallic j...