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Use of Sc2O3 As Etch Stop during Etching of Polysilicon on Thin Dielectrics

IP.com Disclosure Number: IPCOM000119790D
Original Publication Date: 1991-Feb-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 53K

Publishing Venue

IBM

Related People

Hodgson, RT: AUTHOR [+3]

Abstract

In FET technology the polysilicon gate is deposited on a very thin dielectric, usually SiO2, and subsequently the polysilicon is etched to define the gate area. This etching has to stop on the thin dielectric, which, as the technology progresses, may be only a few nm thick. The etching presently usually causes damage to the thin dielectric which has to be repaired later in subsequent processing. It is also possible that in the future the thin gate dielectric may be composed of dual or triple layers additionally involving Si3N4 . This material is even harder to use as an etch stop during gate definition.

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Use of Sc2O3 As Etch Stop during Etching of Polysilicon on Thin Dielectrics

      In FET technology the polysilicon gate is deposited on a very
thin dielectric, usually SiO2, and subsequently the polysilicon is
etched to define the gate area.  This etching has to stop on the thin
dielectric, which, as the technology progresses, may be only a few nm
thick.  The etching presently usually causes damage to the thin
dielectric which has to be repaired later in subsequent processing.
It is also possible that in the future the thin gate dielectric may
be composed of dual or triple layers additionally involving Si3N4 .
This material is even harder to use as an etch stop during gate
definition.

      We have found that a Sc2O3 layer, deposited by sputtering or
alternative methods, etches in CF4 plasmas at a much slower rate than
the above-mentioned dielectrics for all the power conditions
investigated.  Our etch rate data indicate that the etch rate of
Sc2O3 is slower, by at least a factor of 100-1000, than that of SiO2
and Si3N4 .  It should therefore be possible to use this material in
a very thin layer (1-3 nm) as an etch stop during etching of
polysilicon over thin gate dielectrics.  Of course, it is necessary
that this thin layer be compatible with the other requirements of the
gate dielectric.  One of these factors is the dielectric constant.
The higher dielectric constant that this material has (about 8), the
greater the advantage since it increases the capacit...