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Improving I-Cache Access Time for MRU Caches

IP.com Disclosure Number: IPCOM000119793D
Original Publication Date: 1991-Feb-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 45K

Publishing Venue

IBM

Related People

Emma, PG: AUTHOR [+6]

Abstract

In usual terms, the cache is considered to be: a set of congruence classes (CC), each congruence class has a set of associativity (SA), within each CC one of the lines is considered to be MRU.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 80% of the total text.

Improving I-Cache Access Time for MRU Caches

      In usual terms, the cache is considered to be:
   a set of congruence classes (CC),
   each congruence class has a set of associativity (SA),
   within each CC one of the lines is considered to be MRU.

      The ability of a cache to yield a one-cycle access to a
subclass of its lines, the lines that within each congruence class
are MRU, can be effectively made in performance equivalent to one
cycle cache by certain processor organizational features.

      In the special case where the cache is a split I/D cache, the
ability to enhance the probability the target of a Branch Wrong Guess
(BWG) is MRU makes the I-Cache perform like a true one-cycle cache.

      Since the cache is split there are two sets of MRU lines:  the
lines which service the operand accesses and the ones that service
the instruction fetching. In the BHT environment, the access not
being MRU has a reduced impact as the BHT effectively prefetches for
the decoder. However, in the case of a BWG, the non-MRU status of the
corrected target of the branch will create a lost cycle.

      The means associated with avoiding this situation is to promote
to MRU the Next Sequential Line (NSL), if said line is in the cache,
on each global MRU change.  The global MRU line in the cache is the
line that was last referenced.

      Such an approach has the following advantages:
1.  Most taken Branches are short forward branches and will...