Browse Prior Art Database

Improving Infinite Cache Multiprocessor Performance

IP.com Disclosure Number: IPCOM000119794D
Original Publication Date: 1991-Feb-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 45K

Publishing Venue

IBM

Related People

Amos, J: AUTHOR [+6]

Abstract

For processors which maintain the Storage Protect Key (SPK) in the DLATs in order to make it accessible on all relevant cache accesses, the issuance of a SSK (Set Storage Protect Key) instruction requires that all processors in an TCMP configuration to serialize and correct their DLATs concurrently to assure a general consistency with the status of the common memory in the system - a defining characteristic of the TCMP. A second instruction that requires such an action is the IPTE (Invalidate Page Table Entry). For this instruction, the invalidation of the PTE (Page Table Entry) must be accompanied by synchronous invalidation in the DLAT of the processor to assure correctness in the most general situation. The echoing of these instructions by all processors in a TCMP system is unnecessary when the DLAT entries are absent.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 85% of the total text.

Improving Infinite Cache Multiprocessor Performance

      For processors which maintain the Storage Protect Key (SPK) in
the DLATs in order to make it accessible on all relevant cache
accesses, the issuance of a SSK (Set Storage Protect Key) instruction
requires that all processors in an TCMP configuration to serialize
and correct their DLATs concurrently to assure a general consistency
with the status of the common memory in the system - a defining
characteristic of the TCMP.  A second instruction that requires such
an action is the IPTE (Invalidate Page Table Entry). For this
instruction, the invalidation of the PTE (Page Table Entry) must be
accompanied by synchronous invalidation in the DLAT of the processor
to assure correctness in the most general situation.  The echoing of
these instructions by all processors in a TCMP system is unnecessary
when the DLAT entries are absent. By maintaining a secondary copy of
the DLATs for all processors in the SCE and only requiring that the
processor serialize in the event that the SCE indicates the presence
of an affected entry. An ancillary benefit of the second copy is that
the operation within each of the processors including the issuing
processor can be made more efficient by identifying the entries that
require updating rather than searching for them. Thus, on processors
which are affected but have not issued the serializer, the duration
of the impact is shorter.  For the issuing processor, as its DLAT is
available in t...