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Distributed Process Bulletin Board

IP.com Disclosure Number: IPCOM000119797D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 5 page(s) / 149K

Publishing Venue

IBM

Related People

Hailpern, BT: AUTHOR

Abstract

The system described herein is based on the notion of memory-mapped communication between a set of tightly-coupled microprocessors. In multi-microprocessor computer systems, (*) a portion of the memories of some of the several microprocessors is memory-mapped. The memory mapping is practical because memory-access times for the shared memory is commensurate with the microprocessor cycle time. A view of a memory-mapped architecture that can be used as an interprocess communication system with applications to load sharing, task monitoring, and distributed display image processing will now be set forth.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Distributed Process Bulletin Board

      The system described herein is based on the notion of
memory-mapped communication between a set of tightly-coupled
microprocessors.  In multi-microprocessor computer systems, (*) a
portion of the memories of some of the several microprocessors is
memory-mapped.  The memory mapping is practical because memory-access
times for the shared memory is commensurate with the microprocessor
cycle time.  A view of a memory-mapped architecture that can be used
as an interprocess communication system with applications to load
sharing, task monitoring, and distributed display image processing
will now be set forth.

      Consider a system with n+1 processors.  There are n node
microprocessors and a controller, which may be either another
microprocessor or a larger processor.  The memory address space of
each node contains one section that is local (L-section), one section
that is common with a portion of the controller memory that no other
node can access (M-section), and one section that is common with a
portion of the controller's memory that all nodes can access
(S-section).  The controller's address space is also divided into
three sections: its local memory that is not shared with any node, n
blocks of shared memory (each block is shared with exactly 1 node),
and one section of shared memory that is shared with all of the
nodes.  (See Fig. 1.) The implementation of the system consists of
each node's address bus going into a memory-logic module.  That
module connects to the node's local memory and to the appropriate
sections of the controller's memory (on a bus).  The controller's
address space is implemented by physical memory.  (See Fig. 2.)

      The system mechanism is that the nodes will post messages or
information in the portions of their address space that are common
with the controller (M- and S-sections).  The controller can then
process these messages, forward them on to other nodes, and display
them to a user.  We call these shared address spaces a bulletin
board.

      As presented, the bulletin board is partitioned among the n
nodes in a fixed manner.  If the logic module of each node's memory
is programmable, then the partition can be dynamic, depending on the
system's applications and the costs involved.

      Using this bulletin board system we can easily implement an
interprocess communication facility that does not need locking or
synchronization.  The nodes would post messages on the M-sections of
their address space. (Messages of general interest could be posted on
the common S-section.  That would require a protocol as to which
process can post where, so as to avoid overwriting messages. Note
that the common S-section could be partitioned by software convention
in the same way the the M-sections are partitioned by the hardware.)
The controller would read the messages and copy them to the partition
corresponding to the destination node.  In th...